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IBM CPC700 User Manual

IBM CPC700 User Manual (268 pages)

Memory Controller and PCI Bridge

Brand: IBM | Category: Controller | Size: 2.2 MB

Table of Contents

Table of Contents
3
Table of Contents

4
- Figures
  11
Chapter 1. Introduction

17
- Overview
  17
- Figure 1. System Block Diagram
  19
- CPC700 Block Diagram
  20
- Figure 2. Functional Block Diagram
  20
- Table 1. Address Map
  22
- Table 2. PLL Usage
  26
Chapter 2. Signal Descriptions

29
Chapter 3. Processor Interface

37
Chapter 4. Memory Controller

73
Chapter 5. PCI Interface

133
- Overview
  133
- Features
  133
- PCI Bridge Block Diagram
  134
- Figure 38.PCI Interface Macro Block Diagram
  134
- PCI Interface Registers
  135
- Table 39. PCI Interface Local Configuration Registers
  135
- Table 40. PCI Interface Configuration Register Offsets
  135
- PCI Interface Address Maps
  136
  - PLB Address Map
    136
  - Table 41. PLB Address Map
    137
  - PCI Master Map (PMM) Conﬁguration
    138
  - PCI Address Map
    139
  - PCI Target Map (PTM) Conﬁguration
    139
  - Table 42.PCI Memory Address Map
    139
- PCI Target Interface (PLB Master)
  140
  - Commands Generated as PLB Master
    140
  - Handling of Reads from PCI Masters
    141
    
    Read Buffer
    141
    
    Delayed Reads
    141
    
    Read Prefetching
    142
    
    Byte Enable Handling
    142
    
    Handling of Writes from PCI Masters
    142
    
    Byte Enable Handling
    143
  - PCI Request Responses
    143
  - Table 43.PCI Interface Responses to PCI Requests
    143
- PCI Master Interface (PLB Slave)
  145
- Other Bridge Functions
  149
  - Collision Resolution
    149
  - Completion Ordering
    149
    
    Table 45.Collision Resolution
    149
    
    PCI Producer-Consumer Model
    150
  - PCI Frequency Options
    150
    
    Effects on Performance of the Asynchronous Interface
    150
    
    Table 46.PCI Frequency Modes
    150
- Bridge Conﬁguration
  151
  - PCI Interface Local Conﬁguration Register Descriptions
    152
    
    PMM 0 Local Address
    152
    
    Figure 39.Little-Endian
    152
    
    Figure 40.Big-Endian
    152
    
    PMM 0 Mask/Attribute
    153
    
    PMM 0 PCI Low Address
    153
    
    PMM 0 PCI High Address
    153
    
    Table 47.PMM 0 Mask/Attribute Register Bits
    153
    
    PMM 1 Local Address
    154
    
    PMM 1 Mask/Attribute
    154
    
    PMM 1 PCI Low Address
    154
    
    PMM 1 PCI High Address
    154
    
    PMM 2 Local Address
    155
    
    PMM 2 Mask/Attribute
    155
    
    PMM 2 PCI Low Address
    155
    
    PMM 2 PCI High Address
    155
    
    PTM 1 Memory Size/Attribute
    156
    
    PTM 1 Local Address
    156
    
    PTM 2 Memory Size/Attribute
    156
    
    Table 48.PTM 1 Size/Attribute Register Bits
    156
    
    PTM 2 Local Address
    157
  - PCI Conﬁguration Register and Cycles
    157
    
    Conﬁguration Mechanism
    157
    
    Table 49.PTM 2 Size/Attribute Register Bits
    157
    
    PCI Conﬁguration Address Register (PCICFGADR)
    158
    
    PCI Conﬁguration Data Register (PCICFGDATA)
    158
  - PCI Interface Conﬁguration Registers
    158
    
    Figure 41.Format of PCICFGADR Register
    158
    
    PCI Command Register
    159
    
    PCI Device ID Register
    159
    
    PCI Vendor ID Register
    159
    
    Table 50.PCI Command Register Bits
    160
    
    PCI Status Register
    161
    
    Table 51.PCI Status Register Bits
    161
    
    PCI Class Register
    162
    
    PCI Revision ID Register
    162
    
    PCI Cache Line Size
    163
    
    PCI Header Type
    163
    
    PCI Latency Timer
    163
    
    PCI Base Address Register 0 (PCIBAR0)
    164
    
    PCI Base Address Register 1 (PCIPTM1BAR)
    164
    
    PCI Built-In Self Test (BIST) Control
    164
    
    Table 52.PCI BAR 1
    164
    
    PCI Base Address Register 2 (PCIPTM2BAR)
    165
    
    PCI Base Address Registers 3 through 5 (Unused)
    165
    
    PCI Cardbus CIS Pointer (Unused)
    165
    
    PCI Subsystem ID Register
    165
    
    PCI Interrupt Line
    166
    
    PCI Interrupt Pin
    166
    
    Pci Min_Gnt
    166
    
    PCI Subsystem Vendor ID Register
    166
    
    PCI Unused or Reserved
    166
    
    PCI Bus Number
    167
    
    PCI Disconnect Counter
    167
    
    Pci Max_Lat
    167
    
    PCI Subordinate Bus Number
    167
    
    Figure 42.Arbiter Priority Resolution
    168
    
    PCI Arbiter Control
    168
    
    Table 53.PCI Arbiter Control Register Bits
    168
    
    Error Enable
    169
    
    Table 54.Error Enable Register Bits
    169
    
    Bridge Options 1
    170
    
    Error Status
    170
    
    Table 55.Error Status Resister Bits
    170
    
    PLB Slave Error Syndrome Register (SESR)
    171
    
    Table 56.Bridge Options Register Bits
    171
    
    Table 57.Slave Error Syndrome Register Bits
    172
    
    Bridge Options 2
    173
    
    PLB Slave Error Address Register 0 (SEAR0)
    173
    
    PLB Slave Error Address Register 1 (SEAR1)
    173
    
    PCI Initial Target Latency Timer Duration
    174
    
    Table 58.Bridge Options 2 Register Bits
    174
    
    PCI Subsequent Target Latency Timer Duration
    175
- Error Handling
  175
  - Introduction
    175
  - Error Types
    175
  - Table 59.Register Settings
    175
  - Error Descriptions
    176
    
    PLB Unsupported Transfer Type
    176
    
    PCI Master Abort
    176
    
    Table 60.PLB Unsupported Transfer Types
    176
    
    PCI Target Abort Received While PCI Master
    177
    
    PCI Target Data Bus Parity Error Detection
    177
    
    PCI Master Data Bus Parity Error Detection
    178
    
    PCI Address Bus Parity Error While PCI Target
    178
    
    PLB Master Plb_Merr Detection
    179
- Initialization
  179
  - PCI Register Set Initialization
    179
    
    Address Map Initialization
    179
    
    Example Address Map Setup
    180
    
    Figure 43.Example Address Map
    181
    
    Other Registers that Must be Initialized
    182
    
    Target Bridge Initialization
    182
Chapter 6. Clock, Power Management, and Reset

185
- CPC700 Clock Control
  185
  - PLL Tuning
    185
  - Table 61. PLL Usage
    185
  - UART Serial Clock
    186
- Internal Peripheral Power Management
  186
- Reset Control
  186
  - Reset Connectivity
    187
    
    Changes from Earlier Documentation
    188
  - Internal Peripheral Reset Control
    188
- Power on Reset Pin Strapping Options
  188
- Table 62. General Strapping Options
  188
- Table 63. PCI Frequency Modes
  189
- CPR Registers
  190
Chapter 7. UART

195
- Functional Description
  196
- UART Register Description
  197
  - UART Register Summary
    198
    
    Figure 55. Interrupt Enable Register
    198
    
    Table 71. Summary of UART Registers (Big Endian Notation)
    198
    
    Line Control Register
    199
    
    Line Status Register
    200
    
    Table 73. Line Status Register Description
    200
    
    FIFO Control Register
    201
    
    Table 74. FIFO Control Register Description
    201
    
    Interrupt Identiﬁcation Register
    202
    
    Interrupt Enable Register
    203
    
    Divisor Latch LSB and MSB Registers
    204
    
    Scratchpad Register
    204
    
    Table 77. UART Divisor Latch Settings for Certain Baud Rates
    204
- FIFO Operation
  205
  - Interrupt Mode
    205
    
    Receiver
    205
    
    Transmitter
    205
  - Polled Mode
    206
- UART Reset and Sleep Mode
  206
Chapter 8. IIC

207
- Functional Description Overview
  207
- Programming Interface
  207
- Figure 46. 7-Bit Addressing
  207
- IIC Register Map
  208
- Figure 47. 10-Bit Addressing
  208
- Table 78. IIC Registers
  208
- IIC Register Deﬁnitions
  209
  - Master and Slave Data Buffers
    209
  - Lo Master Address Register
    210
  - Table 79. Master Data Buffer
    210
  - Table 80. Master Data Buffer
    210
  - Control Register
    211
  - Table 81. lo Master Address Register
    211
  - Table 82. Hi Master Address Register
    211
  - Table 83. Control Register
    212
  - Table 84. IIC Response to Control Settings
    212
  - Mode Control Register
    213
  - Table 85. Mode Control Register
    213
  - Status Register
    214
  - Table 86. Status Register
    214
  - Extended Status Register Notes
    215
  - Lo Slave Address Register
    216
  - Table 87. Extended Status Register
    216
  - Table 88. lo Slave Address Register
    216
  - Hi Slave Address Register
    217
  - Clock Divide Register
    217
  - Table 89. Hi Slave Address Register
    217
  - Table 90. Clock Divide Register
    217
  - Interrupt Mask Register
    218
  - Transfer Count Register
    218
  - Table 91. IIC Clock Divide Programming
    218
  - Table 92. Interrupt Mask Register
    218
  - Table 93. Transfer Count Register
    219
  - Direct Control Register
    220
  - Table 94. Extended Control and Slave Status Register
    220
- Interrupts
  221
- Table 95. Direct Control Register
  221
- General Considerations
  222
Chapter 9. General Purpose Timers

225
- Introduction
  225
  - GPT Registers
    225
  - Table 96. GPT Registers
    225
  - Programmability
    226
- Mode of Operation
  226
  - Time Base Counter
    226
  - Capture Timers
    227
    
    Capture Timers Interrupt
    227
    
    Figure 48. Capture Timers Logic/Block Diagram
    227
  - Compare Timers
    228
    
    Compare Timers Interrupt
    228
    
    Figure 49. Compare Timer Logic/Block Diagram
    228
  - Interrupt Generation
    229
  - GPT Register Reset Values
    229
  - Table 97. GPT Registers Reset Values
    229
- GPT Detailed Register Description
  230
Chapter 10. Interrupt Controller

235
- Introduction
  235
- Overview
  236
- Interrupt Assignments
  237
- Programmable Conﬁgurability
  237
  - Interrupt Priority Ordering
    237
  - Table 98. Interrupt Assignments
    237
  - Interrupt Vector Base Address
    238
  - Interrupt Enable/Disable
    238
  - INT/MCP Interrupt
    238
  - Polarity
    238
  - Edge/Level Sensitivity
    238
- Universal Interrupt Controller Registers
  238
Chapter 11. JTAG

245
Chapter 12. Processor Local Bus (PLB)

247
Chapter 13. OPB Bridge

251
Chapter 14. Register Summary

253
- CPC700 Registers
  253
  - Processor Interface Registers
    253
  - Table 3. Processor Interface Register Addressing
    253
  - Table 4. Offsets for Processor Interface Registers
    253
  - Memory Controller Registers
    254
  - PCI Interface Registers
    255
  - CPR Registers
    257
  - OPB Bridge Macro Registers
    258
  - Universal Interrupt Controller Registers
    258
  - IIC0 Registers
    258
  - IIC1 Registers
    259
  - UART0 Registers
    260
  - UART1 Registers
    260
  - GPT Registers
    261
Chapter 15. I/O Driver Speciﬁcations

263
Index

265

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