Accelerated Graphics Port (Agp) Controller; Agp Pci Bus Implementation; Figure 1-3; Figure 2-6 - HP X Class 500/550MHz Reference Manual
Personal workstation
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Also See for X Class 500/550MHz:
- User manual (86 pages) ,
- Administrator's manual (118 pages) ,
- Installation manual (60 pages)
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Accelerated Graphics Port (AGP) Controller
Accelerated Graphics Port (AGP) Controller
The AGP technology was developed to provide a dedicated bus for the graphics subsystem,
in order to meet the needs of high quality 3D graphics applications. The HP V
Personal Workstation is equipped with an AGP graphics controller.
The AGP bus is based upon a 66 MHz, 32 Bit PCI bus architecture, to which several signal
groups have been added. These additional signals provide AGP-specific control and
transfer mechanisms:
• Pipelining and sideband addressing. These control mechanisms increase the bus
efficiency in relation to the PCI protocol.
• Double clocking (2x mode). This is a transfer mechanism that doubles the peak transfer
rate to 528 MB/s, as two 32-Bit words are transferred in each clock period (2 x 32 bits x
66 MHz).
AGP specific transactions always use pipelining. The other two mechanisms can combine
independently to pipelining, which leads to the following operating modes:
• FRAME based AGP. Only the PCI protocol is used: 66 MHz, 32 Bits, 3.3V, 264 MB/s
peak transfer rate.
• 1 X AGP with pipelining, sideband addressing can be added: 66 MHz, 32 Bits, 3.3V,
increased bus efficiency, 264 MB/s peak transfer rate.
• 2 X AGP with pipelining, sideband addressing can be added: 66 MHz double clocked, 32
Bits, 3.3V, increased bus efficiency, 528 MB/s peak transfer rate.
AGP PCI Bus Implementation
In the diagram below, the AGP bus is viewed as a PCI bus with extra data lines.
Figure 2-6. AGP PCI Bus Implementation
54
#
PCI Bus
1
AGP
Device
66 MHz
GX-Device 1
AGP Port
Virtual PCI-PCI Bridge
33 MHz
ISUALIZE
Pentium II Xeon Proces-
Intel 440GX - Device 0
Host to PCI Bridge
#
PCI Bus
0
PCI/ISA Bridge
Chapter 2
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