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Chapter 4: Connecting the Emulator to a Target System
Plugging The Emulator Into A Target System
signal meets its required assertion time after power up and clock stabilization. -
Check signal quality on the reset signal, especially the signal transitions.
If some cycles were captured in the trace list, but no cycles are occurring now,
check for setup and hold violations on the processor signals. The "b>" prompt is
not a normal condition for the processor when you find no functional reason. It
usually indicates that the processor has malfunctioned.
If bus cycles are occurring, then the "b>" prompt only indicates that bus cycles are
infrequent. A type of system that would exhibit this behavior would be an
interrupt-driven system. When done processing an interrupt, the system could
execute a STOP instruction to wait for the next interrupt. If the interrupts were
infrequent a "b>" prompt would be displayed.
If the prompt is "w>", the emulator has stopped in the middle of a bus cycle.
To troubleshoot the above problem, you need to know if the target system provides
bus termination for the address. If the answer is no, then the target program must
have run incorrectly. The emulation-bus analyzer will have to be used to
investigate further. If the answer is yes, then you will need to determine the reason
the bus cycle did not complete, as described next.
There are many reasons why bus cycle interaction between a target system and an
emulator may fail. A common cause is that no chip select has been programmed to
assert DSACK internally for the current bus cycle. If the DSACK is generated
external to the processor, another cause is that the target system missed the
start-of-cycle indication from the emulator, or that the emulator missed the
cycle-termination indication from the target system.
A basic MC6833x bus cycle starts with the transfer start signal, AS, and possibly
one or more chip selects. The AS signal stays low throughout the cycle and is
deasserted between cycles. The end of the cycle occurs when the processor
samples a transfer acknowledge DSACK1 or DSACK0 or both, or a transfer error
acknowledge BERR on the falling edge of the clock. A typical system may sample
AS on the rising clock edge and then generate a DSACK signal an integral number
of clocks later. Wait states are added to a cycle by delaying when the DSACK is
asserted.
If there is no functional reason why the bus cycle would not complete, check the
timing relationships between the various bus cycle control signals. Probably the
first measurement you will want to make is to see if the assertion of DSACK is
within the emulator specification.
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